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| NTD6416ANL N-Channel Power MOSFET 100 V, 19 A, 74 mW Features * * * * Low RDS(on) High Current Capability 100% Avalanche Tested These are Pb-Free Devices V(BR)DSS Value 100 $20 19 13 PD IDM TJ, Tstg IS EAS 71 70 -55 to +175 19 50 W A C A mJ 12 TL 260 C 3 G Unit V V A 100 V http://onsemi.com MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Continuous Drain Current Power Dissipation Pulsed Drain Current Steady State Steady State TC = 25C TC = 100C TC = 25C Symbol VDSS VGS ID RDS(on) MAX 74 mW @ 10 V ID MAX 19 A D tp = 10 ms Operating and Storage Temperature Range Source Current (Body Diode) Single Pulse Drain-to-Source Avalanche Energy (VDD = 50 Vdc, VGS = 10 Vdc, IL(pk) = 18.2 A, L = 0.3 mH, RG = 25 W) Lead Temperature for Soldering Purposes, 1/8 from Case for 10 Seconds S 4 4 1 THERMAL RESISTANCE RATINGS Parameter Junction-to-Case (Drain) - Steady State Junction-to-Ambient - Steady State (Note 1) Symbol RqJC RqJA Max 2.1 47 Unit C/W DPAK CASE 369AA STYLE 2 3 IPAK CASE 369D STYLE 2 2 MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain YWW 64 16ANLG 4 Drain YWW 64 16ANLG 3 Source 1 Gate 2 Drain 3 Source Publication Order Number: NTD6416ANL/D Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface mounted on FR4 board using 1 sq in pad size, (Cu Area 1.127 sq in [2 oz] including traces). 1 Gate 2 Drain 6416ANL Y WW G = Device Code = Year = Work Week = Pb-Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. (c) Semiconductor Components Industries, LLC, 2009 October, 2009 - Rev. 0 1 NTD6416ANL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain-to-Source On-Resistance VGS(TH) VGS(TH)/TJ RDS(on) VGS = 4.5 V, ID = 10 A VGS = 10 V, ID = 10 A VGS = 10 V, ID = 19 A Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Plateau Voltage Gate Resistance SWITCHING CHARACTERISTICS (Note 3) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge td(on) tr td(off) tf VSD tRR Ta Tb QRR VGS = 0 V, dIS/dt = 100 A/ms, IS = 19 A TJ = 25C TJ = 125C VGS = 10 V, VDD = 80 V, ID = 19 A, RG = 6.1 W 7.0 16 35 40 0.9 0.72 50 38 14 112 nC ns 1.2 V ns gFS CISS COSS CRSS QG(TOT) QG(TH) QGS QGD VGP RG VGS = 10 V, VDS = 80 V, ID = 19 A VGS = 0 V, f = 1.0 MHz, VDS = 25 V VDS = 5 V, ID = 10 A CHARGES, CAPACITANCES AND GATE RESISTANCE 700 110 50 25 0.7 2.4 9.6 3.2 2.4 V W 40 nC 1000 pF VGS = VDS, ID = 250 mA 1.0 5.4 70 62 68 18 80 74 74 S 2.2 V mV/C mW V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS = 0 V, VDS = 100 V TJ = 25C TJ = 125C VGS = 0 V, ID = 250 mA 100 120 1.0 100 "100 nA V mV/C mA Symbol Test Condition Min Typ Max Unit VDS = 0 V, VGS = "20 V DRAIN-SOURCE DIODE CHARACTERISTICS VGS = 0 V, IS = 19 A 2. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTD6416ANL 40 TJ = 25C ID, DRAIN CURRENT (A) 30 10 V ID, DRAIN CURRENT (A) 4.5 V 3.6 V 20 3.2 V 10 3.0 V 2.8 V 0 VGS = 2.4 V 0 1 2 3 4 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 5 30 40 VDS w 10 V 20 TJ = 125C 10 TJ = 25C TJ = -55C 0 0 1 2 3 4 VGS, GATE-TO-SOURCE VOLTAGE (V) 5 Figure 1. On-Region Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.11 0.1 0.09 0.08 0.07 0.06 ID = 19 A TJ = 25C 0.080 TJ = 25C 0.075 0.070 0.065 0.060 0.055 0.050 VGS = 4.5 V VGS = 10 V 2 4 6 8 10 2 6 10 ID, DRAIN CURRENT (A) 14 18 VGS, GATE-TO-SOURCE VOLTAGE (V) Figure 3. On-Region versus Gate-To-Source Voltage RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 3 VGS = 10 V ID = 19 A IDSS, LEAKAGE (nA) 1000 10000 Figure 4. On-Region versus Drain Current and Gate-To-Source Voltage VGS = 0 V TJ = 150C 2.5 2 1.5 1 TJ = 125C 100 0.5 -50 -25 0 25 50 75 100 125 150 175 10 10 20 30 40 50 60 70 80 90 10 Figure 5. On-Resistance Variation with Temperature TJ, JUNCTION TEMPERTURE (C) Figure 6. Drian-to-Source Leakage Current versus Voltage VDS, DRAIN-TO-SOURCE VOLTAGE (V) http://onsemi.com 3 NTD6416ANL 1400 C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 Crss 0 10 20 30 40 Coss 50 60 70 80 90 Ciss TJ = 25C VGS = 0 V QT VDS, DRAIN-TO-SOURCE VOLTAGE (V) VGS, GATE-TO-SOURCE VOLTAGE (V) 10 8 6 4 Qgs 2 0 VGS VDS Qgd VDS = 80 V ID = 19 A TJ = 25C 0 5 10 15 20 Qg, TOTAL GATE CHARGE (nC) 100 80 60 40 20 0 25 100 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 7. Capacitance Variation 1000 VDS = 80 V ID = 19 A VGS = 10 V Figure 8. Gate-to-Source Voltage and Drain-to-Source Voltage versus Total Charge 20 IS, SOURCE CURRENT (A) TJ = 25C VGS = 0 V 15 t, TIME (ns) 100 td(off) tf tr 10 10 td(on) 5 1 1 10 RG, GATE RESISTANCE (W) 100 0 0.5 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.0 VSD, SOURCE-TO-DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 EAS, SINGLE PULSE DRAIN-TO- SOURCE AVALANCHE ENERGY (mJ) 50 Figure 10. Diode Forward Voltage versus Current ID = 18.2 A 40 30 20 10 0 25 ID, DRAIN CURRENT (A) 10 10 ms 100 ms 1 1 ms 10 ms dc 0.1 0.01 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 VGS = 10 V SINGLE PULSE TC = 25C 100 1000 50 75 100 125 150 175 VDS, DRAIN-TO-SOURCE VOLTAGE (V) VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 11. Resistive Switching Time Variation versus Gate Resistance Figure 12. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 4 NTD6416ANL r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE t1 P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t) t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (ms) 0.01 1.0E-05 1.0E-01 1.0E+00 1.0E+01 Figure 13. Thermal Response ORDERING INFORMATION Device NTD6416ANLT4G NTD6416ANL-1G Package DPAK (Pb-Free) IPAK (Pb-Free) Shipping 2500 / Tape & Reel 75 Units / Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com 5 NTD6416ANL PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA-01 ISSUE A -T- B V R 4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.030 0.045 0.386 0.410 0.018 0.023 0.090 BSC 0.180 0.215 0.024 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.89 0.46 0.61 0.77 1.14 9.80 10.40 0.46 0.58 2.29 BSC 4.57 5.45 0.60 1.01 0.51 --- 0.89 1.27 3.93 --- C E S A 1 2 3 Z H U F L D 2 PL J DIM A B C D E F H J L R S U V Z 0.13 (0.005) M T SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 NTD6416ANL PACKAGE DIMENSIONS DPAK CASE 369D-01 ISSUE B B V R 4 C E Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 --- S -T- SEATING PLANE A 1 2 3 K F D G 3 PL J H M 0.13 (0.005) T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 7 NTD6416ANL/D |
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